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3.8.4
Offset Cancellation
MMA68xx provides the option to read offset cancelled acceleration data via the SPI by clearing the OC bit in the SPI command
(reference Section 4.1 ). A block diagram of the offset cancellation is shown in Figure 20 , and response parameters are specified
in Section 2.4 and in Table 28 .
L PF OUT
Accumulator
Shift
T1
T2
T3
T4
T5
T6
OFFTHR NEG
OFF_ERR
up to 4096 samples
Downsampled to 256 μ s
O FF_ERR
OFFTHR POS
OFF THN
INC
Offset Inc/Dec
OFF CORRP
OFF_CORR_VALUE
OC OUT
OFF THP
DEC
OFF CORRN
Correction
for Start Phase
Figure 20. Offset Cancellation Block Diagram
In normal operation, the offset cancellation circuit computes a 24,576 sample running average of the acceleration data down-
sampled to 256 μ s. The running average is compared against positive and negative thresholds to determine the offset correction
value that will be applied to the acceleration data.
During start up, three phases of moving average sizes are used to allow for faster convergence of misuse input signals. Ref-
erence Table 28 for offset cancellation timing information during startup and normal operation.
Table 28. Offset Cancellation Timing Specifications
Phase
Start Time of
Phase
(from POR)
Typical
Time in Phase
(ms)
# of Samples in
Phase
Samples
Averaged
OFF_CORR_VALUE Averaging Maximum
Update Rate Period Slew Rate
(ms) (ms) (LSB/s)
Averaging Filter
-3dB Frequency
(Hz)
Start 1
Start 2
t OP
t OP + 524.288
524.288
524.288
2048
2048
48
384
2.048
16.38
12.288
98.304
122.1
15.26
36.05
4.506
Start 3 t OP + 1048.576
Normal t OP + 1572.864
524.288
—
2048
—
3072
24576
131.1
1049
786.432
6291.456
1.907
0.2384
0.5632
0.07040
When the self-test circuitry is active, the offset cancellation block and the offset monitor block are suspended, and the offset
correction value is constant. Once the self-test circuitry is disabled, the offset cancellation block remains suspended for the time
t ST_OMB to allow the acceleration output to return to its nominal offset.
3.8.5
Offset Monitor
MMA68xx provides the option for an offset monitor circuit. The offset monitor circuit is enabled when the OFMON bit in the
DEVCFG register is programmed to a logic ‘1’. The output of the offset cancellation circuit is compared against a high and low
threshold. If the offset correction value exceeds either the OFFTHR POS , or OFFTHR NEG threshold, an Offset Over Range con-
dition is indicated.
The offset correction value update rate is listed in Table 28 : “Maximum Slew Rate”. Because the offset monitor uses this value,
the offset monitor will also update at this rate. The time to indicate an Offset Over Range is dependent upon the input signal.
The offset monitor status remains frozen during self-test, because the offset monitor is based on the offset cancellation circuit,
which is also suspended during self-test. The offset monitor is disabled for 2.1 seconds following reset regardless of the state of
the OFMON bit.
3.8.6
Signal Compensation
MMA68xx includes internal OTP and signal processing to compensate for sensitivity error and offset error. This compensation
is necessary to achieve the specified parameters in Section 2.4 .
MMA68xx
Sensors
34
Freescale Semiconductor, Inc.
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